This opening work on chip design which enables digital RF for 5G or high speed fiber communication architect block level design specifications from the marketing requirements and/or system requirements prepare detailed design document, timing constraint file HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL/gate level simulations & silicon

In this line of work, the prospective employee will specialize in high speed analog circuit design for wireline transceivers Determines design approaches and parameters. Analyzes equipment to establish operating data; conducts experimental tests and evaluates results. Selects components and equipment based on analysis of specifications and reliability. May also review ven

Install, configure and run benchmark tests. Identify and troubleshoot system performance bottlenecks. Develop and implement performance testing frameworks and automation tools. Write white papers, blogs on AI solutions with focus on Ethernet fabric Experience with distributed training is a strong plus. Knowledge of Ethernet switching is preferred. The successful candidate

Individual will part of a team that has ownership of key SerDes IP used across multiple products in Broadcom, developed on leading edge silicon technologies. The individual will have ownership for validating one or more aspects of SerDes (Transmitter, Receiver, PLL, CDR) performance at speeds up to 128 Gb/s for PCIE, Ethernet, JESD,CPRI and SAS/SATA standards. Proficient

Work with Business Units chip design team & Analog / Digital IP / Phy owners (e.g. 224G PAM4, 112G PAM4, HBM3/4) for new advanced node silicon (5nm, 3nm, 2nm..) chip floor plan & IP bump pattern design and optimization for package design requirements (e.g. layer count, stack up, escape architecture, BGA pattern development, s parameter extraction/comprehension and optimiz

Overview Of Position As an Account Director, you will drive overall revenue and growth for existing customers in Broadcom's VMware portfolio. This is a quota carrying position located in the San Francisco Bay Area, CA. This position requires you to live in the Bay Area and be onsite for team meetings and attend in person customer meetings. In this role, you'll help Broadc

This position within the Global Technology Organization (GTO) is focused on creating, maintaining and improving the next generation Devops Code Security Scanning tools infrastructure for Broadcom's software development teams. Candidates will be responsible for supporting the needs of multiple product DevOps Teams and organizations across Broadcom while enhancing and suppo

The Elevator Pitch Why would you enjoy this new opportunity? Broadcom is the leader in cloud infrastructure, data center networking and security. We empower customers with solutions from the software defined data center to mobile edge. We have an exciting opportunity for Software Engineer onour Bare Metal Network Security team in the Application Networking and Security Di

Drive in the design, development, document of client side architecture initiatives and product feature development life cycles Drive the process of developing user models, prototyping and crafting user interfaces Build simple to use interfaces for a complex Network & Security solutions Adapt and apply new technologies, best design practices and usability patterns Collabor

Why will you enjoy this new opportunity? Role You will drive performance improvements that will allow customers to further scale their application platforms that build, run and manage their modern workloads across multi and hybrid cloud infrastructure. Product You will work on the Tanzu Application Service (or TAS) which is a cloud platform based on the open source Cloud

Why will you enjoy this new opportunity? You will enable and drive the process for software delivery effectively delivering enterprise software of the highest quality in VMware Tanzu by Broadcom. This role is focused on program management for Tanzu Application Service , our flagship product, and its ecosystem. Job Description As a Principal Engineering Program Manager, yo

Design, optimize, simulate, validate and troubleshoot high speed SERDES channels, 200Gbps and beyond Develop models with EM field solvers (Ansys HFSS, etc) Perform channel margin analysis to provide design tradeoffs between package, PCB and interconnect Work with SERDES IP, Packaging, PCB teams and suppliers on identifying solutions Evaluate board/package materials and co

Work with Business Units chip design team & Analog / Digital IP / Phy owners (e.g. 224G PAM4, 112G PAM4, HBM3/4) for new advanced node silicon (5nm, 3nm, 2nm..) chip floor plan & IP bump pattern design and optimization for package design requirements (e.g. layer count, stack up, escape architecture, BGA pattern development, s parameter extraction/comprehension and optimiz

Job duties include Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re usable testbenches, using the framework of the verification methodology Build pseudo random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and impr

Job duties include Build Test plans with all features for Block/Core/SoC and Write Functional Coverage for the features, participate in Reviews Write scalable and re usable testbenches, using the framework of the verification methodology Develop Psuedo random tests to verify and get to full Functional Coverage Debug Regression failures, analyze Functional coverage gaps an